Many techniques of effectively using a cache have conventionally been provided to improve the processing efficiency of a core. When a core executes a program, the core is allocated with processes constituting the program such as tasks or threads, each of a predetermined unit. The core sequentially executes the processes allocated thereto. A cache included in the core stores data that is used when the core executes the processes. Therefore, when processes that use related data are consecutively allocated to the core, the core can continuously use the data that are stored once in the cache.
On the contrary, when processes that data different from each other are consecutively allocated to the core, the core can not continuously use the data that is stored in the cache. Therefore, a cache-miss may occur. When a cache-miss occurs, the core reads the data necessary for the execution of the processes, from an external memory and stores the new data into the cache when necessary. Therefore, a longer processing time period is necessary compared to a case where the cache is continuously usable.
A technique is disclosed according to which cache-misses are reduced and the processing performance of the core is improved by coordinating in advance the order of executing processes, for the processes that use data stored in a cache to be consecutively executed (see, e.g., Japanese Laid-Open Patent Publication No. 2006-99156).
A technique is also disclosed according to which a process block formed by aggregating a group of processes that are executed using data common thereto is identified, by analyzing a program, dividing the program into plural blocks, and analyzing the relation between inputs and outputs of data among the blocks. For example, the data used when the identified process block is executed are highly related to each other and therefore, reduction of cache-misses can be expected by executing the scheduling for the data stored in the cache to be consecutively executed (see, e.g., Japanese Laid-Open Patent Publication Nos. H10-134030 and 2004-252728).
However, a limitation is present in suppressing occurrence of a cache-miss using the conventional techniques. For example, when the inputs-outputs relation of each of the process blocks is not one to one and data for plural process blocks are necessary for one process block, the same plural process blocks have to be executed and therefore, processes belonging to one same process block alone can not be executed consecutively. Similarly, when a program having complicated dependence relations is executed or when a highly prioritized process or an interrupt by an external process occurs, data different from that for the consecutively executed processes is highly likely to be used and therefore, occurrence of a cache-miss is inevitable.
FIG. 23 is an explanatory diagram of the conventional consecutive execution of processes. FIG. 23 depicts an example of operation of a CPU when the processes are consecutively executed using the conventional techniques. Processes 4, 8, 15, 19, 25, and 29 belonging to a single block are set to be consecutively executed using the conventional techniques.
However, in practice, an external interrupt occurs immediately after the process 4 (step S2301) and an internal interrupt process also occurs (step S2302) as depicted in FIG. 23. Therefore, data stored in a cache for execution of the process 4 is degraded by the processes at steps S2301 and S2302 (a state where other data is stored thereto). Therefore, a cache-miss occurs when the data of the cache is read to execute the process 8.
Similarly, though no interrupt process occurs between the processes 8 and 15, a standby time period occurs to wait for synchronization and a low priority process is executed during the standby time period (step S2303). Another high priority process interrupts and is executed between the processes 15 and 19 (step S2304). As a result, even when the program is analyzed and a setting is made for processes to be executed consecutively, the processes are often not consecutively executed in practice and a cache-miss may occur similarly to the conventional cases.
When a multi-core processor is used that has recently become widely prevalent, an interrupt can be prevented by causing a specific core to execute processes not set such as those at steps S2301 to S2304 of FIG. 23. However, when the multi-core processor is used, one program is efficiently executed and therefore, the process blocks executable in parallel are allocated to different cores for execution.
Therefore, a case may be present where a core #0 executes the process 1 included in an application and another core (for example, a core #1) executes one of the other processes that precede the process 1. In this case, when no other executable process block is present for the core #0, the core #0 has to stand by until the preceding processes executed by the core #1 come to an end.
In an ordinary operating system, during execution of an application, plural applications are often simultaneously executed that have no relation with the application under execution. Therefore, in the operating system, when a standby time period occurs like in the case of the core #0, the processes of the other applications are executed to effectively use the function of the core #0.
In this case, it seems that the processes using the shared data are consecutively executed for each application. However, in practice, the processes of the other applications are executed during the standby time period and therefore, a problem arises in that cache-misses increase.
Setting can be made not to execute any other application during the standby time period. However, as a result of such a setting, the operation of the core is unconditionally stopped during the standby time period. Therefore, a problem arises in that the performance of the entire system is degraded.